Paper Info
Title
Capacity of the MLC NAND Flash Channel.
Abstract
In this paper, we develop a framework for evaluating the symmetric capacity of multilevel-cell (MLC) NAND flash devices while making very few assumptions regarding the underlying device physics. A set of recursive equations are derived that allow one to measure the symmetric capacity for any given page in a flash device using simple conditional statistics that can be extracted experimentally. Using data captured from two different 1y nm MLC devices, we demonstrate that the symmetric capacity of a flash page not only depends on the amount of program/erase cycling and data retention stress that has accumulated, but also on the position of the page within the flash block. We then study the effect on symmetric capacity of using optimized read-back schemes (both hard and soft) and show that while there is significant benefit, not all pages in the block are improved by the same amount. Finally, we show that it is possible to design error correction architectures that harness the inherent variation of symmetric capacity within a flash block to dramatically extend the program/erase cycling endurance of flash-based storage systems.
Year
DOI
Venue
2016
10.1109/JSAC.2016.2603722
IEEE Journal on Selected Areas in Communications
Keywords
Field
DocType
Computer architecture,Microprocessors,Programming,Channel capacity,Error correction codes,Reliability,Threshold voltage
Flash file system,Data retention,Computer science,Communication channel,Real-time computing,NAND gate,Computer hardware,Threshold voltage,Channel capacity,Design Error,Recursion
Journal
Volume
Issue
ISSN
34
9
0733-8716
Citations 
PageRank 
References 
0
0.34
11
Authors
4
Name
Order
Citations
PageRank
Thomas P. Parnell1343.97
Celestine Dunner2126.99
Thomas Mittelholzer312214.32
Nikolaos Papandreou425128.18