Name
Papers
Collaborators
NIKOLAOS PAPANDREOU
42
98
Citations 
PageRank 
Referers 
251
28.18
625
Referees 
References 
1115
304
Search Limit
1001000
Title
Citations
PageRank
Year
AI accelerator on IBM Telum processor: industrial product00.342022
Circuit and System-Level Aspects of Phase Change Memory00.342021
Differentially Private Stochastic Coordinate Descent00.342021
Improving NAND flash performance with read heat separation00.342020
Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash20.372020
SnapBoost: A Heterogeneous Boosting Machine00.342020
Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory40.622019
Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect20.372019
Understanding the Design Trade-Offs of Hybrid Flash Controllers10.352019
Accelerated ML-Assisted Tumor Detection in High-Resolution Histopathology Images.00.342019
Enabling 3D-TLC NAND Flash in Enterprise Storage Systems.00.342018
Benchmarking and Optimization of Gradient Boosted Decision Tree Algorithms.00.342018
Management of Next-Generation NAND Flash to Achieve Enterprise-Level Endurance and Latency Targets.40.442018
Correlating topology and thermodynamics to predict protein structure sensitivity to point mutations.00.342018
From random block corruption to privilege escalation: A filesystem attack vector for rowhammer-like attacks.00.342017
Temporal Correlation Detection Using Computational Phase-Change Memory140.942017
Neuromorphic Architecture With 1M Memristive Synapses for Detection of Weakly Correlated Inputs.20.362017
Recent Progress in Phase-Change Memory Technology.191.252016
Multilevel-Cell Phase-Change Memory: A Viable Technology.120.822016
High-Density Data Storage in Phase-Change Memory.00.342016
Controller architecture for low-latency access to phase-change memory in OpenPOWER systems00.342016
Capacity of the MLC NAND Flash Channel.00.342016
Improving the error-floor performance of binary half-product codes00.342016
Symmetry-based subproduct codes30.442015
Enhancing the Reliability of MLC NAND Flash Memory Systems by Read Channel Optimization70.562015
Performance of cell-to-cell interference mitigation in 1y-nm MLC flash memory00.342015
Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures60.762015
Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems180.822014
Modelling of the threshold voltage distributions of sub-20nm NAND flash memory160.702014
Protein Intrachain Contact Prediction With Most Interacting Residues (Mir)10.362014
A versatile platform for characterization of solid-state memory channels40.802013
Prediction of Chimeric Protein Fold.00.342012
Programming algorithms for multilevel phase-change memory273.572011
Multilevel phase-change memory.50.592010
SPROUTS: a database for the evaluation of protein stability upon point mutation.70.462009
Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator10.372009
A low-complexity bandwidth allocation algorithm for frequency-selective multiuser OFDM systems10.362008
Bit and power allocation in constrained multicarrier systems: the single-user case543.882008
Far-end crosstalk identification method based on channel training sequences20.392005
A new computationally efficient discrete bit-loading algorithm for DMT applications352.342005
From Protocol Models to Their Implementation: A Versatile Testing Methodology20.412004
Transmission Systems Prototyping Based on Stateflow/Simulink Models20.452004