Name
Abstract | ||
|---|---|---|
A novel compact model for on-chip vertically coiled spiral inductors is presented. The vertical metal coils are modeled by a ladder network consisting of ideal inductors and resistors. The skin and proximity effects are taken into consideration. The capacitive parasitics between relevant metal layers are modeled. A method to analytically extract the model parameters is proposed. The model prediction shows excellent agreement between the data from both simulation and measurement over the frequency range of 0.1–66.1 GHz, for a vertically coiled spiral inductor manufactured in TSMC 90 nm RF CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2016 | https://doi.org/10.1007/s10836-016-5613-1 | J. Electronic Testing |
Keywords | Field | DocType |
On-chip,Vertically coiled spiral inductor,Compact model | Computer science,Inductor,Capacitive sensing,Electronic engineering,CMOS,Spiral inductor,Resistor,Parasitic extraction,Model prediction | Journal |
Volume | Issue | ISSN |
32 | 5 | 0923-8174 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bing Hou | 1 | 0 | 0.68 |
| Tong Liu | 2 | 47 | 12.77 |
| jun | 3 | 2 | 2.10 |
| Junli Chen | 4 | 10 | 6.73 |
| Yu Faxin | 5 | 5 | 2.89 |
| Wang Wenbo | 6 | 1200 | 130.70 |