Name
Title | ||
|---|---|---|
Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design. |
Abstract | ||
|---|---|---|
This article proposes a solution to the integrated problem of Through-Silicon Via (TSV) placement and mapping of cores to the routers in a three-dimensional mesh-based Network-on-Chip (NoC) system. TSV geometry restricts their number in three-dimensional (3D) ICs. As a result, only about 25% of routers in a 3D NoC can possess vertical connections. Mapping plays an important role in evolving good system solutions in such a situation. TSVs have been placed with detailed consultation with the application mapping process. The integrated problem was first solved using the exact method of Integer Liner Programming (ILP). Next, a solution was obtained via a Particle Swarm Optimization (PSO) formulation. Several augmentations to the basic PSO strategy have been proposed to generate good-quality solutions. The results obtained are better than many of the contemporary approaches and close to the theoretical situation in which all routers are 3D in nature. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2968446 | ACM Trans. Embedded Comput. Syst. |
Keywords | Field | DocType |
Network-on-chip (NoC),TSV placement,application mapping,3D NoC | Integer,Particle swarm optimization,Polygon mesh,Computer science,Parallel computing,Real-time computing,Through-silicon via,Delegation (computing) | Journal |
Volume | Issue | ISSN |
16 | 1 | 1539-9087 |
Citations | PageRank | References |
3 | 0.43 | 39 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kanchan Manna | 1 | 44 | 5.53 |
| Shivam Swami | 2 | 3 | 0.43 |
| Santanu Chattopadhyay | 3 | 343 | 44.89 |
| Indranil Sengupta | 4 | 498 | 55.11 |