Paper Info
Title
ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing.
Abstract
Scalable Network-on-Chip (NoC) architectures should achieve high-throughput and low-latency operation without exceeding the stringent area/energy constraints of modern Systems-on-Chip (SoC), even when operating under a high clock frequency. Such requirements directly impact the NoC routers and interfaces comprising the NoC architecture. This paper focuses on the micro-architecture of NoC routers and presents ShortPath, a pipelined router architecture that can achieve high-speed implementations by parallelizing as much as possible – and without resorting to speculation – the allocation steps involved in the operation of a VC-based router. Most importantly, ShortPath is augmented with a fine-grained pipeline bypassing mechanism, which skips all stages without contention and “fast-forwards” the flits to the first point of contention. Pipeline bypassing in ShortPath is always productive, and even if a flit loses in arbitration, it does not repeat any of the stages already bypassed. Extensive network simulations and hardware analysis – using standard-cell-based synthesis and placed-and-routed layout – corroborate the efficiency of ShortPath, in terms of both network performance and hardware complexity, as compared to the most relevant current state-of-the-art architecture.
Year
DOI
Venue
2016
10.1109/TC.2016.2519916
IEEE Trans. Computers
Keywords
Field
DocType
Ports (Computers),Computer architecture,Resource management,Pipeline processing,Network-on-chip
Architecture,Pipeline transport,Computer science,Parallel computing,Network on a chip,Real-time computing,Router,Very-large-scale integration,Clock rate,Network performance,Scalability
Journal
Volume
Issue
ISSN
65
10
0018-9340
Citations 
PageRank 
References 
7
0.43
21
Authors
4
Name
Order
Citations
PageRank
Psarras, A.1384.44
Ioannis Seitanidis2163.02
Chrysostomos Nicopoulos383550.37
Giorgos Dimitrakopoulos421527.31