Name
Abstract | ||
|---|---|---|
Imprecise adders are implemented to improve the performance and power consumption of arithmetic circuits with forgivable inaccurate results. These types of designs are extensively used in digital computer systems for approximate computing. One of the challenges in designing imprecise adders is evaluation of output quality. Currently, the most popular technique to evaluate the approximate designs are random simulation and error estimation. These techniques cannot provide exact error analysis. In this paper, we present a formal approach to evaluating the imprecise adders based on BDDs. The proposed framework can measure Exact error rate (EER) of the designs. Additionally, we present a method for test generation (TG) of approximate adders, which can be used for implementing correlation logic. The proposed technique has been demonstrated using a number of imprecise adders (VLSA and ACA) with a large number of errors (over 1 billion). |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISVLSI.2016.85 | 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | Field | DocType |
Imprecise adder,approximate computing,precise error analysis | Boolean function,Adder,Computer science,Word error rate,Measurement uncertainty,Digital computer,Algorithm,Approximate computing,Power consumption,Random simulation | Conference |
ISSN | ISBN | Citations |
2159-3469 | 978-1-4673-9040-8 | 4 |
PageRank | References | Authors |
0.40 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cunxi Yu | 1 | 98 | 9.64 |
| Maciej J. Ciesielski | 2 | 629 | 74.80 |