Paper Info
Title
Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation
Abstract
Post-silicon validation is one of the most important parts of the microprocessor prototype chip lifecycle. It is the last chance for debug engineers to detect defects and bugs that escaped pre-silicon verification, before the chip is released to the market. Effective solutions are required to harness the peak performance of the hardware prototype and evaluate whether the microprocessor chip is fully compliant with the instruction set and other specifications. We perform a comprehensive experimental study on a state-of-the-art microarchitecture to assess and identify the most difficult bugs in address translation caching arrays (multi-level TLBs and MMU Caches), and explain why these bugs persist across generations. We also categorize them into distinct bug scenarios. We then propose a novel methodology for generating random self-checking stimuli programs, which expose and detect such bug scenarios. Our experimental results show that the proposed method can detect difficult bugs that are likely to be missed by traditional post-silicon validation techniques.
Year
DOI
Venue
2016
10.1109/ICCD.2016.7753339
2016 IEEE 34th International Conference on Computer Design (ICCD)
Keywords
Field
DocType
post-silicon validation,silicon debug,design verification,difficult bugs,address translation,virtualization
Post-silicon validation,Instruction set,Computer science,Software bug,Microprocessor,Chip,Real-time computing,Benchmark (computing),Embedded system,Debugging,Microarchitecture
Conference
ISSN
ISBN
Citations 
1063-6404
978-1-5090-5143-4
1
PageRank 
References 
Authors
0.35
12
7
Name
Order
Citations
PageRank
George Papadimitriou1364.38
Gizopoulos, D.21059.80
Athanasios Chatzidimitriou3596.83
Tom Kolan420.71
Anatoly Koyfman5455.97
Ronny Morad6275.57
Vitali Sokhin7262.87