Title
A correction code for multiple cells upsets in memory devices for space applications
Abstract
As the microelectronics technology continuously scales down, the probability of multiple cell upsets (MCUs) induced by radiation in memory devices increases. It is required a robust error correction code (ECC), that has also an area, energy-efficient silicon implementation, to protect electronic devices from MCUs. This article describes the conception, implementation, and evaluation of a new algorithm called CLC, for the detection and correction of multiple errors in memories devices by using extended Hamming and parity bits. The rates of detection and correction of CLC are compared to other correction codes, as well as their implementation cost. The results demonstrated that the CLC has high correction efficiency for MCUs aligned with low area, energy, and delay overhead than the other evaluated codes.
Year
DOI
Venue
2016
10.1109/NEWCAS.2016.7604783
2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)
Keywords
Field
DocType
error correction codes (ECCs),multiple cell upsets,memory devices
Hamming code,Forward error correction,Parity bit,Constant-weight code,Computer science,Turbo code,Robustness (computer science),Electronic engineering,Error detection and correction,Decoding methods
Conference
ISSN
ISBN
Citations 
2472-467X
978-1-4673-8901-3
1
PageRank 
References 
Authors
0.40
0
6