Name
Abstract | ||
|---|---|---|
In this paper we study power, performance, and cost (PPC) tradeoffs for 2-tier, gate-level, full-chip GDS monolithic 3D ICs (M3D) built using a foundry-grade 7nm bulk FinFET technology. We first develop highly-accurate wafer and die cost models for 2D and M3D to study PPC tradeoffs. In our study, both 2D and M3D designs are optimized in terms of the number of BEOL metal layers used for routing to obtain the best possible PPC values. We develop a new CAD methodology for 2-tier gate-level M3D, named Projected 2D Flow, that allows us to accurately compare RC parasitics of equivalent nets in both 2D and M3D designs. Our experiments based on two different circuit types (BEOL-dominant vs. FEOL-dominant) confirm that M3D designs indeed offer a significant footprint saving. However, to our surprise, the PPC quality of M3D turns out to be worse than that of 2D by 34% due to the high wafer cost of M3D. Our study also reveals that M3D wafer yield should be as high as 90% of 2D wafer yield, and the M3D device manufacturing cost should be less than 33% of that of 2D to justify the adoption of M3D technology at the 7nm era. Lastly, and counter-intuitively, our study shows that FEOL-dominant circuit shows more PPC benefits from M3D technology than BEOL-dominant circuit. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2966986.2967044 | ICCAD |
Keywords | Field | DocType |
Monolithic 3D IC,Gate-level,Cost Modeling | CAD,Wafer,Logic gate,Semiconductor device modeling,Computer science,Manufacturing cost,Electronic engineering,Footprint,Parasitic extraction,Cost reduction | Conference |
ISSN | Citations | PageRank |
1933-7760 | 2 | 0.43 |
References | Authors | |
8 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bon Woong Ku | 1 | 18 | 6.01 |
| Peter Debacker | 2 | 32 | 9.04 |
| Dragomir Milojevic | 3 | 111 | 12.25 |
| Praveen Raghavan | 4 | 308 | 47.48 |
| Sung Kyu Lim | 5 | 1688 | 168.71 |