Dragomir Milojevic

Author Info

Name	Affiliation	Papers
DRAGOMIR MILOJEVIC	ULB, Parallel Architectures Real Time Syst PARTS Res C, Brussels, Belgium	25
Collaborators	Citations	PageRank
67	111	12.25
Referers	Referees	References
293	640	263

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100640

Publications (25 rows)

Collaborators (67 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options.	0	0.34	2017
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?	2	0.43	2016
Energy Minimization At All Layers Of The Data Center: The Paradime Project	0	0.34	2016
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.	4	0.53	2016
Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm	1	0.34	2016
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers	4	0.41	2015
A context aware cache controller to bridge the gap between theory and practice in real-time systems	0	0.34	2014
Design issues in heterogeneous 3D/2.5D integration	0	0.34	2013
Panel: "will 3D-IC remain a technology of the future... even in the future?"	1	0.36	2013
Techniques Optimizing the Number of Processors to Schedule Multi-threaded Tasks	32	1.37	2012
U-EDF: An Unfair But Optimal Multiprocessor Scheduling Algorithm for Sporadic Tasks	26	0.99	2012
Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC	2	0.40	2011
Dram-On-Logic Stack - Calibrated Thermal And Mechanical Models Integrated Into Pathfinding Flow	3	0.71	2011
Swapping to reduce preemptions and migrations in EKG	0	0.34	2011
Reducing Preemptions and Migrations in Real-Time Multiprocessor Scheduling Algorithms by Releasing the Fairness	11	0.63	2011
MCDA-based methodology for efficient 3D-design space exploration and decision	0	0.34	2010
On the Design of an Optimal Multiprocessor Real-Time Scheduling Algorithm under Practical Considerations (Extended Version)	1	0.36	2010
Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's.	1	0.37	2010
Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications	7	0.61	2009
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management	5	0.70	2009
Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios	3	0.45	2009
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation	0	0.34	2008
Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms	0	0.34	2008
Power-Aware Real-Time Scheduling upon Identical Multiprocessor Platforms	7	0.54	2008
A framework introducing model reversibility in SoC design space exploration	1	0.36	2007