Paper Info
Title
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms
Abstract
Image features are broadly used in embedded computer vision applications, from object detection and tracking to motion estimation and 3D reconstruction. Efficient feature extraction and description are crucial due to the real-time requirements of such applications over a constant stream of input data. High-speed computation typically comes at the cost of high power dissipation, yet embedded systems are often highly power constrained, making discovery of power-aware solutions especially critical for these systems. In this paper, we present a power and performance evaluation of three low cost feature detection and description algorithms implemented on various embedded systems (embedded CPUs, GPUs and FPGAs). We show that FPGAs in particular offer attractive solutions for both performance and power and describe several design techniques utilized to accelerate feature extraction and description algorithms on low-cost Zynq SoC FPGAs.
Year
DOI
Venue
2016
10.1109/FPL.2016.7577310
2016 26th International Conference on Field Programmable Logic and Applications (FPL)
Keywords
Field
DocType
feature detection algorithm,feature description algorithms,embedded computer vision applications,object detection,object tracking,motion estimation,3D reconstruction,feature extraction,low-cost Zynq SoC FPGA
Computer science,Real-time computing,Motion estimation,3D reconstruction,Object detection,Algorithm design,Feature (computer vision),Parallel computing,Field-programmable gate array,Algorithm,Feature extraction,Hardware acceleration,Embedded system
Conference
ISSN
ISBN
Citations 
1946-1488
978-1-5090-0851-3
5
PageRank 
References 
Authors
0.46
16
5
Name
Order
Citations
PageRank
Onur Ulusel1121.34
Christopher Picardo250.80
Christopher B. Harris3182.48
Sherief Reda4128392.25
R. Iris Bahar587884.31