Title
Design considerations for 50G+ backplane links.
Abstract
The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.
Year
Venue
Keywords
2016
Proceedings of the European Solid-State Circuits Conference
wireline,IO link,backplane,equalization,CTLE,feed-forward equalizer,FFE,decision-feedback equalizer,DFE,MLSE,ADC,56G,Ethernet,TCM,THP,PAM-4
Field
DocType
ISSN
Backplane,Computer science,Electronic engineering,Bandwidth (signal processing),Data rate,Jitter,Attenuation
Conference
1930-8833
Citations 
PageRank 
References 
0
0.34
12
Authors
11
Name
Order
Citations
PageRank
Thomas Toifl127548.02
Matthias Braendli215824.28
Alessandro Cevrero310716.21
Pier Andrea Francese413825.33
Marcel A. Kossel517933.86
Lukas Kull614118.63
Danny Luu7167.55
Christian Menolfi824541.54
Thomas Morf924442.54
Ilter Özkaya10165.72
Hazar Yueksel1174.15