A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET | 0 | 0.34 | 2019 |
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET | 2 | 0.40 | 2019 |
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. | 0 | 0.34 | 2018 |
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. | 1 | 0.35 | 2018 |
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. | 1 | 0.48 | 2017 |
DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. | 0 | 0.34 | 2017 |
High-speed link with trellis-coded modulation and Reed-Solomon coding | 0 | 0.34 | 2016 |
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. | 0 | 0.34 | 2016 |
23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. | 2 | 0.43 | 2016 |
Design considerations for 50G+ backplane links. | 0 | 0.34 | 2016 |
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver | 1 | 0.46 | 2015 |