Paper Info
Title
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.
Abstract
This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation.
Year
Venue
Field
2016
Proceedings of the European Solid-State Circuits Conference
32-bit,Timing failure,OpenRISC,Computer science,Microprocessor,Electronic engineering,Chip,Digital clock manager,CPU multiplier,Speedup
DocType
ISSN
Citations 
Conference
1930-8833
0
PageRank 
References 
Authors
0.34
6
6
Name
Order
Citations
PageRank
Jeremy Constantin1404.86
Andrea Bonetti2145.89
Adam Teman312919.12
Christoph Muller420.72
Lorenz Schmid500.34
A. Burg61426126.54