Name
Title | ||
|---|---|---|
A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration |
Abstract | ||
|---|---|---|
A 100MS/s 10-bit ADC design using a 130nm standard CMOS technology is presented in this paper. The proposed design adopted the split capacitor array digital-to-analog converter (DAC) to build successive approximation register (SAR) analog-to-digital converter (ADC) structure using a single input. On-chip mismatch calibration feature is utilized to compensate the capacitor mismatches of the DAC and to calibrate the input offset voltage of a comparator. The proposed calibration uses a simple and efficient algorithm and optimizes the capacitor mismatches of the DAC by using inverter-based capacitor comparison technique and by controlling additional auxiliary capacitor arrays in calibration mode. The ADC achieves 41.9dB of SNR and consumes 1.1mW with 1.2V supply voltage. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/NATW.2016.9 | 2016 IEEE 25th North Atlantic Test Workshop (NATW) |
Keywords | Field | DocType |
successive approximation register (SAR) ADC,spilt-capacitor array DAC,built-in calibration (BIC),offset calibration,capacitor mismatch compensation | Inverter,Capacitor,Comparator,Input offset voltage,Voltage,CMOS,Electronic engineering,Successive approximation ADC,Engineering,Electrical engineering,Calibration | Conference |
ISBN | Citations | PageRank |
978-1-4673-8950-1 | 0 | 0.34 |
References | Authors | |
10 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yongsuk Choi | 1 | 16 | 6.01 |
| Yong-bin Kim | 2 | 338 | 55.72 |
| In-Seok Jung | 3 | 18 | 5.12 |