Name
Abstract | ||
|---|---|---|
Racetrack memory is a promising non-volatile memory because of its ultra-high storage density. The data are stored along the tape-like cell, where a “shift” operation is used to move the data in a cell back and forth to be accessed. Shift operations suffer from “position error”, where the shift distance is incorrect. Previous work solved the error by position error correction code (p-ECC). However, a bit error within the p-ECC bits will fail the correction mechanism. To protect p-ECC bits from bit errors, we propose a new mapping method for p-ECC, called nonadjacent position error correction code (np-ECC) in this paper. Evaluation shows significant reduction on correction mechanism failure rate. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2950067.2950082 | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
Keywords | Field | DocType |
Racetrack memory,Error Correction Code,Position Error | Code rate,Constant-weight code,Soft error,Computer science,Parallel computing,Failure rate,Error detection and correction,FX.25 Forward Error Correction,Racetrack memory,Bit error rate | Conference |
ISSN | ISBN | Citations |
2327-8218 | 978-1-4673-8927-3 | 0 |
PageRank | References | Authors |
0.34 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaoyang Wang | 1 | 3 | 0.74 |
| Chao Zhang | 2 | 423 | 38.17 |
| Xian Zhang | 3 | 53 | 12.42 |
| Guangyu Sun | 4 | 1920 | 111.55 |