Name
Abstract | ||
|---|---|---|
1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1 trillion instructions/sec while dissipating 13.1 W. |
Year | Venue | Field |
|---|---|---|
2016 | Symposium on VLSI Circuits-Digest of Papers | Orders of magnitude (numbers),Computer science,Processor array,Parallel computing,Chip,Electronic engineering,CMOS,Computer hardware,Computation,Embedded system |
DocType | Citations | PageRank |
Conference | 10 | 0.48 |
References | Authors | |
0 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Brent Bohnenstiehl | 1 | 33 | 3.90 |
| Aaron Stillmaker | 2 | 61 | 5.12 |
| Jon J. Pimentel | 3 | 58 | 4.50 |
| Timothy Andreas | 4 | 31 | 2.15 |
| Bin Liu | 5 | 1281 | 68.98 |
| Anh Tran | 6 | 49 | 7.14 |
| Emmanuel Adeagbo | 7 | 31 | 2.15 |
| Bevan M. Baas | 8 | 295 | 27.78 |