Title
A Survey of Techniques for Architecting and Managing GPU Register File
Abstract
To support their massively-multithreaded architecture, GPUs use very large register file (RF) which has a capacity higher than even L1 and L2 caches. In total contrast, traditional CPUs use tiny RF and much larger caches to optimize latency. Due to these differences, along with the crucial impact of RF in determining GPU performance, novel and intelligent techniques are required for managing GPU RF. In this paper, we survey the techniques for designing and managing GPU RF. We discuss techniques related to performance, energy and reliability aspects of RF. To emphasize the similarities and differences between the techniques, we classify them along several parameters. The aim of this paper is to synthesize the state-of-art developments in RF management and also stimulate further research in this area.
Year
DOI
Venue
2017
10.1109/TPDS.2016.2546249
IEEE Trans. Parallel Distrib. Syst.
Keywords
Field
DocType
Radio frequency,Graphics processing units,Registers,Random access memory,Reliability,Message systems,Power demand
Power management,Architecture,Efficient energy use,Latency (engineering),Computer science,Register file,Real-time computing,Radio frequency,Power demand,General-purpose computing on graphics processing units,Distributed computing
Journal
Volume
Issue
ISSN
28
1
1045-9219
Citations 
PageRank 
References 
2
0.42
0
Authors
1
Name
Order
Citations
PageRank
Sparsh Mittal181750.36