Name
Title | ||
|---|---|---|
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. |
Abstract | ||
|---|---|---|
Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phaselocked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate be... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCSI.2016.2609855 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Phase locked loops,Clocks,Jitter,Bandwidth,Frequency synthesizers,Phase noise,Limit-cycles | Phase-locked loop,Control theory,Delay-locked loop,Phase noise,Frequency synthesizer,Electronic engineering,Voltage-controlled oscillator,Delta-sigma modulation,Jitter,Direct digital synthesizer,Mathematics | Journal |
Volume | Issue | ISSN |
64 | 2 | 1549-8328 |
Citations | PageRank | References |
1 | 0.36 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Romesh Kumar Nandwana | 1 | 45 | 10.36 |
| Saurabh Saxena | 2 | 174 | 16.84 |
| Amr Elshazly | 3 | 242 | 28.08 |
| Kartikeya Mayaram | 4 | 349 | 58.50 |
| Pavan Kumar Hanumolu | 5 | 554 | 84.82 |