Name
Abstract | ||
|---|---|---|
This paper presents a novel scan-based design for test (DFT) paradigm. Compared with conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage or allows applying a much larger number of vectors within the same time interval. An equally important factor is the toggling activity during test-with this scheme, it remains similar t... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2016.2608984 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Clocks,Built-in self-test,Circuit faults,Computer architecture,Discrete Fourier transforms,Registers | Design for testing,Fault coverage,Computer science,Scan chain,Test data compression,Electronic engineering,Real-time computing,Test compression,Built-in self-test | Journal |
Volume | Issue | ISSN |
25 | 3 | 1063-8210 |
Citations | PageRank | References |
7 | 0.52 | 28 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Grzegorz Mrugalski | 1 | 501 | 35.90 |
| Janusz Rajski | 2 | 2460 | 201.28 |
| Jĕdrzej Solecki | 3 | 28 | 4.07 |
| Jerzy Tyszer | 4 | 838 | 74.98 |
| Chen Wang | 5 | 253 | 15.83 |