Name
Title | ||
|---|---|---|
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. |
Abstract | ||
|---|---|---|
A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2016.2580713 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
Clocks,Random access memory,Phase locked loops,Jitter,Bandwidth,Delays,Graphics | Dram,Phase-locked loop,Computer science,Communication channel,Real-time computing,Electronic engineering,CMOS,Chip,Bandwidth (signal processing),Interference (wave propagation),Jitter,Computer hardware | Journal |
Volume | Issue | ISSN |
25 | 1 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Junyoung Song | 1 | 40 | 11.42 |
| Hyun-Woo Lee | 2 | 0 | 0.34 |
| Sewook Hwang | 3 | 41 | 10.43 |
| Chulwoo Kim | 4 | 397 | 74.58 |