Name
Abstract | ||
|---|---|---|
The utilization of block RAMs (BRAMs) is a critical performance factor for multiported memory designs on field-programmable gate arrays (FPGAs). Not only does the excessive demand on BRAMs block the usage of BRAMs from other parts of a design, but the complex routing between BRAMs and logic also limits the operating frequency. This paper first introduces a brand new perspective and a more efficient way of using a conventional two reads one write (2R1W) memory as a 2R1W/4R memory. By exploiting the 2R1W/4R as the building block, this paper introduces a hierarchical design of 4R1W memory that requires 25% fewer BRAMs than the previous approach of duplicating the 2R1W module. Memories with more read/write ports can be extended from the proposed 2R1W/4R memory and the hierarchical 4R1W memory. Compared with previous xor-based and live value table-based approaches, the proposed designs can, respectively, reduce up to 53% and 69% of BRAM usage for 4R2W memory designs with 8K-depth. For complex multiported designs, the proposed BRAM-efficient approaches can achieve higher clock frequencies by alleviating the complex routing in an FPGA. For 4R3W memory with 8K-depth, the proposed design can save 53% of BRAMs and enhance the operating frequency by 20%. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2016.2568579 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
Field programmable gate arrays,Random access memory,Memory management,Ports (Computers),Routing,Registers,Logic gates | Registered memory,Interleaved memory,Semiconductor memory,Extended memory,Computer science,Non-volatile random-access memory,Parallel computing,Electronic engineering,Memory management,Flat memory model,Computer memory | Journal |
Volume | Issue | ISSN |
25 | 1 | 1063-8210 |
Citations | PageRank | References |
5 | 0.52 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bo-Cheng Charles Lai | 1 | 177 | 19.25 |
| Jiun-Liang Lin | 2 | 7 | 0.95 |