Paper Info
Title
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation.
Abstract
When dealing with partially reconfigurable designs on field-programmable gate array, floorplanning represents a critical step that highly impacts system’s performance and reconfiguration overhead. However, current vendor design tools still require the floorplan to be manually defined by the designer. Within this paper, we provide a novel floorplanning automation framework, integrated in the Xilinx tool chain, which is based on an explicit enumeration of the possible placements of each region. Moreover, we propose a genetic algorithm (GA), enhanced with a local search strategy, to automate the floorplanning activity on the defined direct problem representation. The proposed approach has been experimentally evaluated with a synthetic benchmark suite and real case studies. We compared the designed solution against both the state-of-the-art algorithms and alternative engines based on the same direct problem representation. Experimental results demonstrated the effectiveness of the proposed direct problem representation and the superiority of the defined GA engine with respect to the other approaches in terms of exploration time and identified solution.
Year
DOI
Venue
2017
10.1109/TVLSI.2016.2562361
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
Field programmable gate arrays,Automation,Engines,Genetic algorithms,Algorithm design and analysis,Performance evaluation,Very large scale integration
Algorithm design,Computer science,Field-programmable gate array,Automation,Electronic engineering,Gate array,Local search (optimization),Genetic algorithm,Control reconfiguration,Floorplan
Journal
Volume
Issue
ISSN
25
1
1063-8210
Citations 
PageRank 
References 
5
0.55
17
Authors
5
Name
Order
Citations
PageRank
Marco Rabozzi1417.58
Gianluca Durelli2307.13
Antonio Miele334533.18
John Lillis420415.62
Marco D. Santambrogio577191.15