Name
Abstract | ||
|---|---|---|
Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1016/j.microrel.2016.07.116 | Microelectronics Reliability |
Keywords | Field | DocType |
Reliability evaluation,Probabilistic transfer matrix,Digital circuits | Digital electronics,Computer science,Circuit design,Combinational logic,Transfer matrix,Probabilistic logic,Electronic circuit,Reliability engineering,Computation | Journal |
Volume | ISSN | Citations |
64 | 0026-2714 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hao Cai | 1 | 60 | 21.94 |
| Kaikai Liu | 2 | 190 | 20.37 |
| Lirida A. B. Naviner | 3 | 83 | 26.52 |
| You Wang | 4 | 29 | 9.66 |
| Mariem Slimani | 5 | 23 | 7.05 |
| J. Naviner | 6 | 12 | 3.88 |