You Wang - Citegraph

Author Info

Name	Affiliation	Papers
YOU WANG	Département Communications et ElectroniqueInstitut Mines-TélécomTélécom-ParisTechLTCI-CNRS-UMR 5141Paris CEDEX 1375634France	26
Collaborators	Citations	PageRank
57	29	9.66
Referers	Referees	References
73	396	166

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100396

Publications (26 rows)

Collaborators (57 rows)

Referers (73 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Spinsim: A Computer Architecture-Level Variation Aware Stt-Mram Performance Evaluation Framework	0	0.34	2021
A Reconfigurable Arbiter Puf Based On Stt-Mram	0	0.34	2021
Fully Single Event Double Node Upset Tolerant Design For Magnetic Random Access Memory	0	0.34	2021
Spin-Orbit Torque Nonvolatile Flip-Flop Designs	0	0.34	2021
A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM	0	0.34	2020
Compact Modeling And Analysis Of Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction	0	0.34	2020
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI	0	0.34	2019
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.	0	0.34	2019
Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes	0	0.34	2019
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction	0	0.34	2019
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.	0	0.34	2018
A high-reliability and low-power computing-in-memory implementation within STT-MRAM.	1	0.44	2018
MRAM-on-FDSOI Integration: A Bit-Cell Perspective	0	0.34	2018
Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.	8	0.53	2017
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.	0	0.34	2017
Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core	0	0.34	2017
Efficient reliability evaluation methodologies for combinational circuits.	0	0.34	2016
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.	0	0.34	2016
A novel circuit design of true random number generator using magnetic tunnel junction	4	0.46	2016
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters.	0	0.34	2016
Approximate computing in MOS/spintronic non-volatile full-adder	3	0.38	2016
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects.	3	0.46	2015
Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction	7	0.56	2015
Robust magnetic full-adder with voltage sensing 2T/2MTJ cell	0	0.34	2015
Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology.	0	0.34	2015
Compact thermal modeling of spin transfer torque magnetic tunnel junction	3	0.40	2015