Name
Title | ||
|---|---|---|
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs. |
Abstract | ||
|---|---|---|
In this paper we investigate the effects of asymmetric organization and depths of Network-on-Chip (NoC) router buffers among dies in heterogeneous 3D-System-on-Chips (SoCs). In our novel approach the properties of the routers are aligned with the characteristics of the technological nodes per layer. We call these designs Asymmetric 3D-NoCs (A-3D-NoCs). In this work we demonstrate potentials of A-3D-NoCs in comparison to a conventional, symmetric 3D-NoC: Applying asymmetric buffer reorganization we achieve area savings of 8.3% and power savings of 5.4% for link buffers while accepting a minor average system performance loss of 2.1%. With additional asymmetry in buffer depth up to 28% cost savings and 15% power reduction are given in combination with a 4.6% performance decline. Thus, the proposed buffer organization scheme is applicable for cost and power critical applications of NoCs in heterogeneous 3D-SoCs. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1016/j.micpro.2016.09.011 | Microprocessors and Microsystems |
Keywords | Field | DocType |
Network-on-Chip,Heterogeneous 3D-System-on-Chip,Asymmetric 3D-Noc,Buffer reorganization,Buffer depths | Computer science,Parallel computing,Network on a chip,Computer network,Real-time computing,Router | Journal |
Volume | ISSN | Citations |
48 | 0141-9331 | 1 |
PageRank | References | Authors |
0.38 | 27 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jan Moritz Joseph | 1 | 20 | 9.01 |
| christopher blochwitz | 2 | 7 | 3.27 |
| Alberto García-Ortiz | 3 | 66 | 19.23 |
| Thilo Pionteck | 4 | 90 | 26.99 |