Title
Using just-in-time code generation for transparent resource management in heterogeneous systems
Abstract
Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads.
Year
DOI
Venue
2016
10.1109/RTSI.2016.7740545
2016 IEEE 2nd International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow (RTSI)
Keywords
Field
DocType
just-in-time code generation,transparent resource management,hardware accelerators,academia,industry,multicore plus accelerator,SAVEHSA architecture,heterogeneous hardware platform,PCIe,GPGPU,FPGA,Intel MIC,parallel processing,workload distribution,resource allocation
Resource management,Xeon Phi,Computer science,Code generation,Resource allocation,PCI Express,Component-based software engineering,Multi-core processor,Operating system,Embedded system,Executable
Conference
ISBN
Citations 
PageRank 
978-1-5090-1132-2
0
0.34
References 
Authors
9
8