Paper Info
Title
Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches
Abstract
In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in on-chip caches. Although STT-RAMs benefit from high-density, non-volatility, and low-power characteristics, high rates of read disturbances and write failures are the major reliability problems in STTRAM caches. These disturbance/failure rates are directly affected not only by workload behaviors, but also by process variations. Several studies characterized the reliability of STTRAM caches just for one cell, but vulnerability of STT-RAM caches cannot be directly derived from these models. This paper extrapolates the reliability characteristics of one STTRAM cell presented in previous studies to the vulnerability analysis of STT-RAM caches. To this end, we propose a highlevel framework to investigate the vulnerability of STT-RAM caches affected by the per-cell disturbance/failure rates as well as the workloads behaviors and process variations. This framework is an augmentation of gem5 simulator. The investigation reveals that: 1) the read disturbance rate in a cache varies by 6 orders of magnitude for different workloads, 2) the write failure rate varies by 4 orders of magnitude for different workloads, and 3) the process variations increase the read disturbance and write failure rates by up to 5.8x and 8.9x, respectively.
Year
DOI
Venue
2016
10.1109/EDCC.2016.10
2016 12th European Dependable Computing Conference (EDCC)
Keywords
Field
DocType
Process Variations (PVs),Read Disturbance,STT-RAM Cache,Write Failure
Cache,Workload,Vulnerability assessment,Computer science,Failure rate,Real-time computing,Vulnerability
Conference
ISBN
Citations 
PageRank 
978-1-5090-1583-2
1
0.36
References 
Authors
12
4
Name
Order
Citations
PageRank
Elham Cheshmikhani1123.60
Amir Mahdi Hosseini Monazzah2326.89
Hamed Farbeh3479.85
Seyed Ghassem Miremadi453150.32