Name
Title | ||
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NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. |
Abstract | ||
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With the recent reincarnations of neuromorphic computing comes the promise of a new computing paradigm, with a focus on the design and fabrication of neuromorphic chips. A key challenge in design, however, is that programming such chips is difficult. This paper proposes a systematic methodology with a set of tools to address this challenge. The proposed toolset is called NEUTRAMS (<u>Neu</u>ral network <u>Tra</u>nsformation, <u>M</u>apping and <u>S</u>imulation), and includes three key components: a neural network (NN) transformation algorithm, a configurable clock-driven simulator of neuromorphic chips and an optimized runtime tool that maps NNs onto the target hardware for better resource utilization. To address the challenges of hardware constraints on implementing NN models (such as the maximum fan-in/fan-out of a single neuron, limited precision, and various neuron models), the transformation algorithm divides an existing NN into a set of simple network units and retrains each unit iteratively, to transform the original one into its counterpart under such constraints. It can support both spiking neural networks (SNNs) and traditional artificial neural networks (ANNs), including convolutional neural networks (CNNs) and multilayer perceptrons (MLPs) and recurrent neural networks (RNNs). With the combination of these tools, we have explored the hardware/software co-design space of the correlation between network error-rates and hardware constraints and consumptions. Doing so provides insights which can support the design of future neuromorphic architectures. The usefulness of such a toolset has been demonstrated with two different designs: a real Complementary Metal-Oxide-Semiconductor (CMOS) neuromorphic chip for both SNNs and ANNs and a processing-in-memory architecture design for ANNs.
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Year | DOI | Venue |
|---|---|---|
2016 | 10.5555/3195638.3195663 | MICRO-49: The 49th Annual IEEE/ACM International Symposium on Microarchitecture
Taipei
Taiwan
October, 2016 |
Keywords | Field | DocType |
NEUTRAMS toolset,neural network transformation mapping and simulation,neural network co-design,neuromorphic hardware constraints,neuromorphic computing,neuromorphic chip fabrication,neural network transformation algorithm,configurable clock-driven simulator,optimized runtime tool,resource utilization,spiking neural networks,artificial neural networks,convolutional neural networks,multilayer perceptrons,recurrent neural networks,hardware software co-design,network error-rates | Convolutional neural network,Computer science,Parallel computing,Recurrent neural network,Neuromorphic engineering,Chip,Software,Artificial neural network,Spiking neural network,Perceptron | Conference |
ISBN | Citations | PageRank |
978-1-4503-4952-9 | 6 | 0.44 |
References | Authors | |
36 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yu Ji | 1 | 16 | 2.24 |
| Youhui Zhang | 2 | 202 | 28.36 |
| Shuangchen Li | 3 | 636 | 36.82 |
| Ping Chi | 4 | 183 | 6.34 |
| Cihang Jiang | 5 | 6 | 0.44 |
| Peng Qu | 6 | 13 | 2.68 |
| Yuan Xie | 7 | 6430 | 407.00 |
| Wenguang Chen | 8 | 1014 | 70.57 |