Name
Affiliation
Papers
YOUHUI ZHANG
Microprocessor & SoC Research Center, Tsinghua Univ., Beijing, P.R.C
67
Collaborators
Citations 
PageRank 
126
202
28.36
Referers 
Referees 
References 
649
1752
595
Search Limit
1001000
Title
Citations
PageRank
Year
EcoForecast: An interpretable data-driven approach for short-term macroeconomic forecasting using N-BEATS neural network00.342022
A review of basic software for brain-inspired computing00.342022
Accelerating Neural Network Training with Processing-in-Memory GPU00.342022
Polyhedral-Based Compilation Framework for In-Memory Neural Network Accelerators00.342022
A Reduced Architecture for ReRAM-Based Neural Network Accelerator and Its Software Stack10.352021
Regu2D - Accelerating Vectorization of SpMV on Intel Processors through 2D-partitioning and Regular Arrangement.00.342021
AIPerf: Automated machine learning as an AI-HPC benchmark20.362021
SuSy: a programming model for productive construction of high-performance systolic arrays on FPGAs10.362020
ERA-LSTM: An Efficient ReRAM-Based Architecture for Long Short-Term Memory30.382020
High Performance Simulation of Spiking Neural Network on GPGPUs10.352020
A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration00.342019
FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture70.432019
Programmable Neural Network Trojan for Pre-Trained Feature Extractor.00.342019
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis20.502019
TETRIS - TilE-matching the TRemendous Irregular Sparsity.00.342018
In-Place Irregular Computation for Message-Passing Chip-Multiprocessors00.342017
Parallel Turing Machine, a Proposal.20.422017
Hardware support for message-passing in chip multi-processors.10.352017
POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware00.342017
Service-Oriented Architecture on FPGA-Based MPSoC.100.582017
Modelling Spiking Neural Network from the Architecture Evaluation Perspective.20.352016
Neural network transformation under hardware constraints.10.342016
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.60.442016
Optimized Mapping Spiking Neural Networks onto Network-on-Chip.30.372016
Near Data Computation For Message-Passing Chip-Multiprocessors00.342016
Software-Based Lightweight Multithreading to Overlap Memory-Access Latencies of Commodity Processors.00.342015
Position-aware thread-level speculative parallelization for large-scale chip-multiprocessor00.342015
Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable Platforms70.512015
An approach of processor core customization for stencil computation10.392014
Customized Network-on-Chip for Message Reduction.00.342014
Cache Optimizations of Distributed Storage for Software Streaming Services10.382013
Employing intelligence in object-based storage devices to provide attribute-based file access190.412013
Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memory331.002013
Software/Hardware Hybrid Network-on-Chip Simulation on FPGA.20.392013
HW/SW approaches to accelerate GRAPES in an FU array00.342013
Accelerating solvers for global atmospheric equations through mixed-precision data flow engine131.102013
Automatic software deployment using user-level virtualization for cloud-computing100.562013
A Performance Model for Network-on-Chip Wormhole Routers.30.392012
Employing Object-Based Storage Devices To Embed File Access Control In Storage00.342011
Using User-Level Virtualization in Desktop Grid Clients for Application Delivery and Sandboxing00.342011
Model Of Network-On-Chip Routers And Performance Analysis40.482011
A user-space file system for on-demand legacy desktop software.00.342011
A Performance Analytical Approach Based on Queuing Model for Network-on-Chip10.362010
Converting legacy desktop applications into on-demand personalized software40.482010
Efficient Monte Carlo-based options pricing on graphics processors and its optimizations.10.602010
Codec-On-Demand Based On User-Level Virtualization00.342009
Optimized Mapping Of Pixels Into Memory For H.264/Avc Decoding00.342009
On Virtual-Machine-Based Windows File Reads: A Performance Study00.342008
IDRS: Combining File-level Intrusion Detection with Block-level Data Recovery based on iSCSI20.392008
Portable desktop applications based on user-level virtualization00.342008
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