Name
Abstract | ||
|---|---|---|
Recently, we must use the various scan test techniques for various purposes, for example, compression scan or LBST for mass-production test, LBIST for field test, legacy scan for fault diagnosis, and so on. Moreover, the number of the available external scan pins is different in each test process, for example, the parallel test process has a low pin count, the assembled chip test process has several pin counts depending on the assembled package types, and so on. Then, the cost-effective scan chain structure is also different for each purpose and each test process. In order to correspond to this situation, we introduce the multi-configuration scan structure which can change the numbers of scan chains. Evaluation result shows that our approach can improve test time for area overhead. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ATS.2016.32 | 2016 IEEE 25th Asian Test Symposium (ATS) |
Keywords | Field | DocType |
scan testing,multi-mode scan,cost-effective testing | Boundary scan,Structured systems analysis and design method,Computer science,Scan chain,Chip,Real-time computing,Low Pin Count,Computer hardware,Test compression,Embedded system | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-5090-3810-7 | 1 |
PageRank | References | Authors |
0.38 | 0 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Iwata | 1 | 3 | 0.79 |
| Jun Matsushima | 2 | 13 | 4.09 |