Name
Abstract | ||
|---|---|---|
The paper proposes a Scan Chain Adaptation Through ECO (SCATE) methodology to accommodate scan chain changes at advanced physical design stage into the existing DFT compression logic and eliminates the need of re-running the complete scan insertion flow. With the proposed methodology scan chain changes can be implemented as ECO to achieve cycle time reduction with minimum overhead. It can handle last minute changes due to the addition of new scan chains or changes in scan chain lengths in existing IPs. The scope of the work is also extended to reduce the cycle time of a derivative product from a base design. Results from industrial designs in 28FDSOI and 40nm CMOS technologies show SOC test coverage of above 99% when new scan chains were included using the proposed methods. Test time gain of more than 30% was observed by adjusting the maximum scan chain lengths. Use of SCATE methodology enabled DFT modifications through ECO and saved design cycle time by avoiding loopback to fresh DFT insertion, Timing analysis and Physical design flows in industrial SOCs |
Year | Venue | Field |
|---|---|---|
2016 | ATS | Code coverage,Loopback,Computer science,Scan chain,Electronic engineering,Real-time computing,CMOS,Static timing analysis,Physical design,Codec,Embedded system,Design cycle |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jasvir Singh | 1 | 8 | 4.21 |
| Anuj Grover | 2 | 10 | 6.49 |
| Mausumi Pohit | 3 | 1 | 1.03 |
| Anurag Singh Baghel | 4 | 0 | 0.34 |
| Gurjit Kaur | 5 | 0 | 0.34 |
| Shalini Pathak | 6 | 0 | 0.34 |