Author Info
Name
Affiliation
Papers
ANUJ GROVER
STMicroelectronics, Greater Noida, India
17
Collaborators
Citations 
PageRank 
63
10
6.49
Referers 
Referees 
References 
39
288
84
Search Limit
100288
Title
Citations
PageRank
Year
ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices10.392021
A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology00.342018
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.20.402017
Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies.00.342017
LoCCo-Based Scan Chain Stitching for Low-Power DFT.10.362017
Scan Chain Adaptation through ECO.00.342016
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework00.342016
A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications00.342016
New stable loadless 6T dual-port SRAM cell design00.342016
Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques.00.342016
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI00.342016
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation00.342016
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs10.382015
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems10.382015
Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance10.392015
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F MAX tracking00.342014
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology30.832013