Paper Info
Title
An Ultra-High-Speed Test Module and FPGA-Based Development Platform
Abstract
This paper describes a low-cost extension module used to extend an FPGA-based development platform that enables digital testing up to 40Gbps. This platform typically operates up to 13.1Gbps and can be applied to test current main-stream I/O standards such as PCIE3.0 (8Gbps), USB3.1 (10Gbps) and Thunderbolt (10Gbps). The high bandwidth of an ultra-high-speed test module allows testing capability for future high-speed standards such as PCIE4.0 (32Gbps) and 40G Ethernet. An FPGA main board is built and programmed to control this plugin module for testing at across a wide range of data-rates. Using such "state of the art" FPGAs and careful design strategy of an economical FR4 plugin board, the data rate is extended to 40Gbps. This economical plugin module is implemented by multiplexing four high-speed channels from the FPGA into a single 40Gbps serial bit stream.
Year
DOI
Venue
2016
10.1109/ATS.2016.26
2016 IEEE 25th Asian Test Symposium (ATS)
Keywords
Field
DocType
ATE,FPGA,High-speed I/O,DUT,Multi-GHz
Design strategy,Transceiver,Computer science,Field-programmable gate array,Communication channel,Electronic engineering,Real-time computing,Ethernet,Plug-in,Multiplexing,Bitstream,Embedded system
Conference
ISSN
ISBN
Citations 
1081-7735
978-1-5090-3810-7
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Te-Hui Chen131.41
David C. Keezer26817.00