Name
Abstract | ||
|---|---|---|
The increasing complexity of new digital signal processing (DSP) applications is forcing the use of floating point (FP) numbers in their hardware implementations. In this brief, we investigate the advantages of using half-unit biased (HUB) formats to implement these FP applications on field-programmable gate arrays (FPGAs). These new FP formats allow for the effective elimination of the rounding l... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCSII.2016.2563798 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Digital signal processing,Field programmable gate arrays,Computer architecture,Standards,Adders,Finite impulse response filters,Signal to noise ratio | Digital signal processing,Adder,Computer science,Floating point,Signal-to-noise ratio,Field-programmable gate array,Electronic engineering,Rounding,Implementation,Computer hardware,Fpga implementations | Journal |
Volume | Issue | ISSN |
64 | 3 | 1549-7747 |
Citations | PageRank | References |
1 | 0.36 | 12 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Javier Hormigo | 1 | 113 | 19.45 |
| Julio Villalba | 2 | 219 | 23.56 |