Name
Abstract | ||
|---|---|---|
Placing the DRAM in the same package as a processor enables several times higher memory bandwidth than conventional off-package DRAM. Yet, the latency of in-package DRAM is not appreciably lower than that of off-package DRAM. A promising use of in-package DRAM is as a large cache. Unfortunately, most previous DRAM cache designs optimize mainly for cache hit latency and do not consider bandwidth efficiency as a first-class design constraint. Hence, as we show in this paper, these designs are suboptimal for use with in-package DRAM.
We propose a new DRAM cache design, Banshee, that optimizes for both in-package and off-package DRAM bandwidth efficiency without degrading access latency. Banshee is based on two key ideas. First, it eliminates the tag lookup overhead by tracking the contents of the DRAM cache using TLBs and page table entries, which is efficiently enabled by a new lightweight TLB coherence protocol we introduce. Second, it reduces unnecessary DRAM cache replacement traffic with a new bandwidth-aware frequency-based replacement policy. Our evaluations show that Banshee significantly improves performance (15% on average) and reduces DRAM traffic (35.8% on average) over the best-previous latency-optimized DRAM cache design.
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Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3123939.3124555 | MICRO-50: The 50th Annual IEEE/ACM International Symposium on Microarchitecture
Cambridge
Massachusetts
October, 2017 |
Keywords | DocType | Volume |
DRAM Cache, Main Memory, In-Package DRAM, Hybrid Memory Systems, TLB Coherence, Cache Replacement | Conference | abs/1704.02677 |
ISSN | ISBN | Citations |
1072-4451 | 978-1-4503-4952-9 | 20 |
PageRank | References | Authors |
0.60 | 39 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiangyao Yu | 1 | 270 | 16.17 |
| Christopher J. Hughes | 2 | 988 | 63.34 |
| Nadathur Satish | 3 | 2020 | 99.88 |
| Onur Mutlu | 4 | 9446 | 357.40 |
| Srinivas Devadas | 5 | 8606 | 1146.30 |