| Orchestrating Data Placement and Query Execution in Heterogeneous CPU-GPU DBMS. | 0 | 0.34 | 2022 |
| Lotus: Scalable Multi-Partition Transactions on Single-Threaded Partitioned Databases. | 0 | 0.34 | 2022 |
| Pushdowndb: Accelerating A Dbms Using S3 Computation | 0 | 0.34 | 2020 |
| A Retrospective on Path ORAM | 0 | 0.34 | 2020 |
| LiTM - A Lightweight Deterministic Software Transactional Memory System. | 1 | 0.37 | 2019 |
| SCAR: Strong Consistency using Asynchronous Replication with Minimal Coordination. | 0 | 0.34 | 2019 |
| Rethinking Database High Availability with RDMA Networks. | 0 | 0.34 | 2019 |
| Choosing A Cloud DBMS: Architectures and Tradeoffs. | 1 | 0.35 | 2019 |
| FastDAWG - Improving Data Migration in the BigDAWG Polystore System. | 0 | 0.34 | 2018 |
| STAR: Scaling Transactions through Asymmetrical Replication. | 0 | 0.34 | 2018 |
| Sundial: harmonizing concurrency control and caching in a distributed OLTP database management system | 1 | 0.35 | 2018 |
| Banshee: Bandwidth-Efficient DRAM Caching Via Software/Hardware Cooperation. | 20 | 0.60 | 2017 |
| Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. | 0 | 0.34 | 2016 |
| Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models. | 6 | 0.42 | 2016 |
| TicToc: Time Traveling Optimistic Concurrency Control. | 27 | 0.72 | 2016 |
| A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. | 0 | 0.34 | 2016 |
| A Proof of Correctness for the Tardis Cache Coherence Protocol | 4 | 0.40 | 2015 |
| PrORAM: dynamic prefetcher for oblivious RAM | 12 | 0.61 | 2015 |
| TARDIS: Timestamp based Coherence Algorithm for Distributed Shared Memory. | 4 | 0.40 | 2015 |
| Tardis: Time Traveling Coherence Algorithm for Distributed Shared Memory. | 9 | 0.46 | 2015 |
| Tardis 2.0: An Optimized Time Traveling Coherence Protocol. | 0 | 0.34 | 2015 |
| Optimizing Path ORAM for Cloud Storage Applications. | 0 | 0.34 | 2015 |
| IMP: indirect memory prefetcher | 28 | 0.82 | 2015 |
| Staring into the abyss: an evaluation of concurrency control with one thousand cores | 10 | 0.49 | 2014 |
| Design and Evaluation of Hierarchical Rings with Deflection Routing | 10 | 0.52 | 2014 |
| Unified Oblivious-RAM: Improving Recursive ORAM with Locality and Pseudorandomness. | 10 | 0.63 | 2014 |
| Suppressing The Oblivious Ram Timing Channel While Making Information Leakage And Program Efficiency Trade-Offs | 6 | 0.49 | 2014 |
| Enhancing Oblivious RAM Performance Using Dynamic Prefetching. | 4 | 0.40 | 2014 |
| Generalized external interaction with tamper-resistant hardware with bounded information leakage | 11 | 0.59 | 2013 |
| Design space exploration and optimization of path oblivious RAM in secure processors | 47 | 1.37 | 2013 |
| A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches | 3 | 0.40 | 2013 |
| Integrity Verification For Path Oblivious-Ram | 11 | 0.53 | 2013 |
| MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect | 45 | 1.21 | 2012 |
