Name
Abstract | ||
|---|---|---|
High capacity and scalable memory systems play a vital role in enabling our desktops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately, memory systems are becoming increasingly prone to faults. This is because we rely on technology scaling to improve memory density, and at small feature sizes, memory cells tend to break easily. Today, memory reliability is seen as the key impediment towards using high-density devices, adopting new technologies, and even building the next Exascale supercomputer. To ensure even a bare-minimum level of reliability, present-day solutions tend to have high performance, power and area overheads. Ideally, we would like memory systems to remain robust, scalable, and implementable while keeping the overheads to a minimum. This dissertation describes how simple cross-layer architectural techniques can provide orders of magnitude higher reliability and enable seamless scalability for memory systems while incurring negligible overheads. |
Year | Venue | Field |
|---|---|---|
2017 | arXiv: Hardware Architecture | Uniform memory access,Supercomputer,Computer science,Parallel computing,Distributed memory,Computing with Memory,Real-time computing,Memory geometry,Embedded system,Moore's law,Scalability,Overhead (business) |
DocType | Volume | Citations |
Journal | abs/1704.03991 | 0 |
PageRank | References | Authors |
0.34 | 27 | 1 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Prashant J. Nair | 1 | 346 | 15.74 |