Name
Title | ||
|---|---|---|
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. |
Abstract | ||
|---|---|---|
This paper proposes a SAT-based formulation to evaluate the logical capacity of VIA-configurable block templates. The proposed solution is able to support any user-defined regular layout. The proposed SAT formulation was sucessufully applied to the three main VCSA fabrics in the literature considering transistor networks from an open cell library and transistor networks representing all 4-input Bo... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TETC.2016.2644381 | IEEE Transactions on Emerging Topics in Computing |
Keywords | Field | DocType |
Layout,Fabrics,Lithography,Transistors,Integrated circuits,Shape | Boolean function,Quadratic growth,Computer science,Boolean satisfiability problem,Parallel computing,Algorithm,Application-specific integrated circuit,Real-time computing,Template,Transistor,Integrated circuit | Journal |
Volume | Issue | ISSN |
5 | 2 | 2168-6750 |
Citations | PageRank | References |
0 | 0.34 | 21 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinícius Dal Bem | 1 | 19 | 4.07 |
| Felipe S. Marranghello | 2 | 21 | 6.50 |
| André Inácio Reis | 3 | 134 | 21.33 |
| Renato P. Ribas | 4 | 204 | 33.52 |