Paper Info
Title
Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark
Abstract
AbstractThe discrete event system specification formalism, which supports hierarchical and modular model composition, has been widely used to understand, analyze and develop a variety of systems. Discrete event system specification has been implemented in various languages and platforms over the years. The DEVStone benchmark was conceived to generate a set of models with varied structure and behavior, and to automate the evaluation of the performance of discrete event system specification-based simulators. However, DEVStone is still in a preliminary phase and more model analysis is required. In this paper, we revisit DEVStone introducing new equations to compute the number of events triggered. We also introduce a new benchmark with a similar central processing unit and memory requirements to the most complex benchmark in DEVStone, but with an easier implementation and with it being more manageable analytically. Finally, we compare both the performance and memory footprint of five different discrete event system specification simulators in two different hardware platforms.
Year
DOI
Venue
2017
10.1177/0037549717690447
Periodicals
Keywords
Field
DocType
Discrete event system specification,DEVStone,synthetic benchmarks,performance,memory usage
Central processing unit,Discrete event system,Simulation,Computer science,Modeling and simulation,Model composition,Parallel computing,Real-time computing,DEVS,Modular design,Formalism (philosophy),Memory footprint
Journal
Volume
Issue
ISSN
93
6
0037-5497
Citations 
PageRank 
References 
4
0.42
2
Authors
5
Name
Order
Citations
PageRank
José L. Risco-Martín124431.13
Saurabh Mittal223923.42
Juan Carlos Fabero Jiménez361.10
marina zapater45410.70
Román Hermida58915.34