Name
Abstract | ||
|---|---|---|
Timing analysis in embedded systems has focused mainly on the Worst-Case Execution Time (WCET) in the past. This was (and still is) important to make guarantees for the application of the system in safety critical environments. Today, two reasons call for a slightly changed perspective. Firstly, the complex and often unpredictable internal structure of modern system-on-chip architectures prohibits the calculation of realistic upper bounds for the WCET. Secondly, even if we can compute a realistic value for the WCET, the developer still does not know how the code under scrutiny behaves in general and whether it is useful or necessary to spend time on optimising this code. In this contribution, we present a new method and hardware architecture to collect Execution Time Profiles (ETP) which give us much more insight in the execution time behaviour on modern system-on-chip architectures as previously available. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISORC.2017.16 | 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC) |
Keywords | Field | DocType |
timing analysis,performance analysis,(re) configurable architectures,FPGA,embedded systems,histograms,execution time profiles | Histogram,Know-how,Computer science,Automaton,Field-programmable gate array,Real-time computing,Static timing analysis,Execution time,Distributed computing,Embedded system,Hardware architecture | Conference |
ISBN | Citations | PageRank |
978-1-5386-1575-1 | 0 | 0.34 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas Ballenthin | 1 | 0 | 0.68 |
| Boris Dreyer | 2 | 3 | 0.73 |
| Christian Hochberger | 3 | 457 | 99.51 |
| Simon Wegener | 4 | 9 | 3.53 |