| Towards Purposeful Design Space Exploration Of Heterogeneous Cgras: Clock Frequency Estimation | 0 | 0.34 | 2020 |
| Improving HLS Generated Accelerators Through Relaxed Memory Access Scheduling | 0 | 0.34 | 2020 |
| Engineering an Optimized Instruction Set Architecture for AMIDAR Processors. | 0 | 0.34 | 2020 |
| Update or Invalidate - Influence of Coherence Protocols on Configurable HW Accelerators. | 0 | 0.34 | 2019 |
| Non-Intrusive Online Timing Analysis of Large Embedded Applications. | 0 | 0.34 | 2019 |
| UltraSynth - Integration of a CGRA into a Control Engineering Environment. | 0 | 0.34 | 2019 |
| AutoBoxing: Improving GCC Passes to Optimize HW/SW Multi-Versioning of Kernels for HLS | 0 | 0.34 | 2019 |
| Iterative Histogram-based Performance Analysis of Embedded Systems | 0 | 0.34 | 2019 |
| A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications | 1 | 0.36 | 2018 |
| Online Analysis Of Debug Trace Data Or Embedded Systems | 3 | 0.39 | 2018 |
| Fast DSE for Automated Parallelization of Embedded Legacy Applications. | 0 | 0.34 | 2018 |
| Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling. | 0 | 0.34 | 2018 |
| AutoStreams: Fully Automatic parallelization of Legacy Embedded Applications with Soft-Core MPSoCs | 0 | 0.34 | 2018 |
| Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems. | 5 | 0.46 | 2017 |
| A Near Optimal Integrated Solution for Resource Constrained Scheduling, Binding and Routing on CGRAs | 0 | 0.34 | 2017 |
| Hardware Support for Histogram-Based Performance Analysis of Embedded Systems | 0 | 0.34 | 2017 |
| ReEP: A Toolset for Generation and Programming of Reconfigurable Datapaths for Event Processing | 1 | 0.37 | 2017 |
| Scheduler for Inhomogeneous and Irregular CGRAs with Support for Complex Control Flow | 2 | 0.39 | 2016 |
| Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs. | 0 | 0.34 | 2016 |
| RapidSoC: short turnaround creation of FPGA based SoCs. | 0 | 0.34 | 2016 |
| A readback based general debugging framework for soft-core processors | 0 | 0.34 | 2016 |
| Feasibility of high level compiler optimizations in online synthesis | 3 | 0.40 | 2015 |
| Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation | 3 | 0.40 | 2015 |
| GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs | 2 | 0.38 | 2015 |
| Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs | 0 | 0.34 | 2014 |
| Runtime verification for multicore SoC with high-quality trace data | 14 | 0.77 | 2013 |
| Polymorphic Computers - Virtualization of Instruction Set and Microarchitecture. | 0 | 0.34 | 2013 |
| Register Allocation For High-Level Synthesis Of Hardware Accelerators Targeting Fpgas | 1 | 0.37 | 2013 |
| Custom reconfigurable architecture based on virtex 5 lookup tables | 1 | 0.36 | 2013 |
| Towards GCC-based automatic soft-core customization. | 2 | 0.40 | 2012 |
| Influence of operating conditions on ring oscillator-based entropy sources in FPGAs. | 2 | 0.49 | 2012 |
| Exploring online synthesis for CGRAs with specialized operator sets | 3 | 0.66 | 2011 |
| Still Image Processing on Coarse-Grained Reconfigurable Array Architectures | 1 | 0.35 | 2010 |
| Low-Complexity Online Synthesis for AMIDAR Processors. | 1 | 0.36 | 2010 |
| A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor | 2 | 0.39 | 2010 |
| Effects of Simplistic Online Synthesis for AMIDAR Processors | 1 | 0.36 | 2009 |
| Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings | 24 | 2.31 | 2009 |
| Challenges of Electronic CAD in the Nano Scale Era | 0 | 0.34 | 2009 |
| Towards Dynamic Software/Hardware Transformation In Amidar Processors | 1 | 0.36 | 2008 |
| Architecture of Computing Systems - ARCS 2008, 21st International Conference, Dresden, Germany, February 25-28, 2008, Proceedings | 20 | 2.07 | 2008 |
| Dynamic Web-Page Generation in Resource-Constrained Environments The Kertasarie Server Pages | 0 | 0.34 | 2008 |
| Rekonfigurierbare Architekturen | 0 | 0.34 | 2008 |
| A New Methodology For Debugging And Validation Of Soft Cores | 1 | 0.39 | 2008 |
| A resource optimized Processor Core for FPGA based SoCs | 12 | 0.92 | 2007 |
| Predicting Hardware Acceleration Through Object Caching in AMIDAR Processors | 1 | 0.36 | 2006 |
| Automatisierte Erzeugung von TTCN-3 Testfiällen aus UML-Modellen | 0 | 0.34 | 2006 |
| Informatik 2006 - Informatik für Menschen, Band 1, Beiträge der 36. Jahrestagung der Gesellschaft für Informatik e.V. (GI), 2.-6. Oktober 2006 in Dresden | 184 | 45.26 | 2006 |
| ARCS 2006 - 19th International Conference on Architecture of Computing Systems, Workshops Proceedings, March 16, 2006, Frankfurt am Main, Germany | 38 | 9.95 | 2006 |
| 18th International Conference on Architecture of Computing Systems, Workshops, Innsbruck, Austria, March 2005 | 19 | 4.61 | 2005 |
| The AMIDAR Class of Reconfigurable Processors | 17 | 1.02 | 2005 |
