Name
Abstract | ||
|---|---|---|
Null Convection Logic is a well-known paradigm for designing asynchronous logic circuits. The conventional CMOS-based NCL designs suffers larger area overhead and power consumption. A low power design technique called Gate Diffusion Input (GDI) has been adopted to overcome this limitation. In GDI technology, voltage swing exhibits significant voltage drop across the circuit. Therefore, not suitable for designing large combinational circuits. A novel HYBRID (CMOS+GDI) design is proposed in this work to efficiently address this issue. The HYBRID design utilizes both CMOS and GDI technology to reduce the number of transistor and power dissipation when compared to CMOS NCL circuits. The proposed approach is implemented in NCL Ripple Carry Adder (RCA) and simulated in Cadence Virtuoso for verification. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISOCC.2016.7799749 | 2016 International SoC Design Conference (ISOCC) |
Keywords | Field | DocType |
combinational circuits,Cadence Virtuoso,RCA,ripple carry adder,power dissipation,HYBRID design,CMOS-GDI design,voltage drop,voltage swing,gate diffusion input,low power design technique,power consumption,area overhead,CMOS-based NCL design,asynchronous logic circuit,null convection logic,area/power reduction,hybrid GDI-NCL | Logic gate,Adder,Computer science,Electronic engineering,Combinational logic,CMOS,Electronic circuit,Transistor,Integrated injection logic,Electrical engineering,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
2163-9612 | 978-1-5090-3220-4 | 0 |
PageRank | References | Authors |
0.34 | 5 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Prashanthi Metku | 1 | 0 | 2.70 |
| Ramu Seva | 2 | 0 | 1.69 |
| Kyung Ki Kim | 3 | 99 | 21.62 |
| Yong-Bin Kim | 4 | 22 | 7.14 |
| Minsu Choi | 5 | 156 | 27.63 |