| Optimization of Null Convenction Logic Using Gate Diffusion Input | 0 | 0.34 | 2019 |
| Area Efficient Multi-Threshold Null Convenction Logic | 0 | 0.34 | 2019 |
| Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation | 0 | 0.34 | 2019 |
| Evaluations of Electronic Neuron Model for Low Power VLSI Implementation | 0 | 0.34 | 2019 |
| Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing | 0 | 0.34 | 2018 |
| Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique | 0 | 0.34 | 2018 |
| Clothing-based wearable sensors for unobtrusive interactions with mobile devices | 0 | 0.34 | 2017 |
| Time-Domain Temperature Sensor Based On Interlaced Hysteresis Delay Cells | 0 | 0.34 | 2017 |
| Fully Integrated on-Chip Switched DC-DC Converter for Battery-Powered Mixed-Signal SoCs. | 0 | 0.34 | 2017 |
| Low-power null convention logic design based on modified gate diffusion input technique | 0 | 0.34 | 2017 |
| Cooperation of multi robots for disaster rescue | 0 | 0.34 | 2017 |
| Low power asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) | 0 | 0.34 | 2017 |
| Variable bit truncation technique for approximate stochastic computing (ASC) | 0 | 0.34 | 2017 |
| Parallel decoding for multi-stage BCH decoder | 0 | 0.34 | 2016 |
| Hybrid GDI-NCL for area/power reduction | 0 | 0.34 | 2016 |
| A Flexible Software Defined Radio-Based Uhf Rfid Reader Based On The Usrp And Labview | 0 | 0.34 | 2016 |
| Current Mode Four-Quadrant Multiplier Design Using Cntfet | 0 | 0.34 | 2016 |
| An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction | 1 | 0.40 | 2016 |
| Approximate stochastic computing (ASC) for image processing applications | 0 | 0.34 | 2016 |
| A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters | 1 | 0.43 | 2014 |
| Power Switch Implementation For Low Voltage Digital Circuits | 0 | 0.34 | 2013 |
| A novel 4-to-3 step-down on-chip SC DC-DC converter with reduced bottom-plate loss | 1 | 0.36 | 2012 |
| On-chip HBD sensor for nanoscale CMOS technology | 1 | 0.36 | 2012 |
| A design and integration of Parametric Measurement Unit on to a 600MHz DCL | 0 | 0.34 | 2012 |
| All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter | 0 | 0.34 | 2012 |
| Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits | 7 | 2.11 | 2011 |
| Adaptive Power Management For Nanoscale Soc Design | 0 | 0.34 | 2011 |
| A design approach of a Parametric Measurement Unit on to a 600MHz DCL | 0 | 0.34 | 2011 |
| Dynamic Voltage And Frequency Scaling For Power-Constrained Design Using Process Voltage And Temperature Sensor Circuits | 2 | 0.37 | 2011 |
| On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits | 33 | 1.52 | 2010 |
| Adaptive HCI-aware power gating structure | 2 | 0.40 | 2010 |
| Hybrid MOSFET/CNFET based power gating structure. | 0 | 0.34 | 2010 |
| A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems | 12 | 1.17 | 2009 |
| Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage | 7 | 0.56 | 2009 |
| A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates | 0 | 0.34 | 2009 |
| Standby Power Reduction Using Optimal Supply Voltage And Body-Bias Voltage | 4 | 0.60 | 2008 |
| Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels | 2 | 0.45 | 2008 |
| Low power CMOS electronic central pattern generator design for a biomimetic underwater robot | 13 | 1.01 | 2007 |
| Optimal Body Biasing for Minimum Leakage Power in Standby Mode | 4 | 0.55 | 2007 |
| Leakage Minimization Technique for Nanoscale CMOS VLSI | 2 | 0.51 | 2007 |
| Ultra-Low Voltage High-Speed Schmitt Trigger Circuit In Soi Mosfet Technology | 2 | 0.50 | 2007 |
| A Cmos Low Power Fully Digital Adaptive Power Delivery System Based On Finite State Machine Control | 0 | 0.34 | 2007 |
| Modeling And Analysis Of Inter-Symbol Interference (Isi) Jitter | 0 | 0.34 | 2007 |
| Data Dependent Jitter (DDJ) Characterization Methodology | 1 | 0.38 | 2005 |
| On the Modeling and Analysis of Jitter in ATE Using Matlab | 4 | 0.80 | 2005 |
