Name
Abstract | ||
|---|---|---|
This paper proposes presents a low power and highspeed four-quadrant analog multiplier in the current mode based on dual translinear loops using 32nm CMOS and 32nm CNTFET technologies to investigate and compare the performance differences of the analog circuits on CNTFET technology and CMOS 32nm technology nodes. All the simulations were performed using hspice with 32nm CMOS from PTM library and 32nm CNTFET from Stanford University technologies at the same power supply level. CNTFET based multiplier shows a wider linearity over considerable range of outputs (-10 mu A to +10 mu A) while the CMOS based multiplier shows (-7 mu A to +7 mu A) and the 3db frequency of the CNTFET based multiplier is 110GHz while the 3dB frequency of the CMOS based multiplier is only 2.45GHz. |
Year | Venue | Keywords |
|---|---|---|
2016 | 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | Carbon Nano Tube FET(CNTFET), multiplier design, low power circuits, emerging technology |
Field | DocType | ISSN |
Logic gate,Analog multiplier,Analogue electronics,Computer science,Linearity,Electronic engineering,Multiplier (economics),CMOS,Bandwidth (signal processing),Carbon nanotube field-effect transistor,Electrical engineering | Conference | 2163-9612 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gyunam Jeon | 1 | 1 | 1.41 |
| Minsu Choi | 2 | 156 | 27.63 |
| Kyung Ki Kim | 3 | 99 | 21.62 |
| Yong-Bin Kim | 4 | 22 | 7.14 |