Name
Abstract | ||
|---|---|---|
Scan chain architecture is a common and major DFT for SoCs. Scan chains must be flawless for reliable SoC test. If there is a fault in a scan chain, eliminating the fault and its cause is important for high yield of SoC. In this paper, a new scan chain diagnosis method, "p-backtracking", is proposed. This method uses only software to backtrack the logic circuit and calculates the probability of fault in scan chain. The experimental results using ISCAS'89 benchmark circuits show that p-backtracking can find single fault location with higher diagnosis accuracy and smaller diagnosis resolution compared to the conventional diagnosis methods. |
Year | Venue | Keywords |
|---|---|---|
2016 | 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | Scan chain diagnosis, probability, backtraking |
Field | DocType | ISSN |
Logic gate,Computer science,Scan chain,Real-time computing,Software,Electronic circuit,Backtracking,Benchmark (computing) | Conference | 2163-9612 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tae Hyun Kim | 1 | 359 | 29.05 |
| Hyunyul Lim | 2 | 0 | 0.34 |
| Sungho Kang | 3 | 436 | 78.44 |