Name
Abstract | ||
|---|---|---|
To get a reasonable yield, memories incorporate redundancies to substitute for faulty cells. As the performance of repair algorithm reaches some saturation point, recent studies focus on various redundancy architectures for higher repair rate. In this paper, three kinds of spares, i.e., local, common, and global spares, are discussed to analyze the efficiency of redundancy architectures in respect of the repair cost. In order to estimate the impact of each spare, more than a hundred redundancy architectures are simulated with different faulty patterns. This paper performs a data analysis and suggests cost-effective redundancy architectures. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISOCC.2016.7799751 | 2016 International SoC Design Conference (ISOCC) |
Keywords | Field | DocType |
built-in redundancy analysis (BIRA),repair cost,yield,redundancy architecture | Algorithm design,Spare part,Active redundancy,Computer science,Triple modular redundancy,Theoretical computer science,Real-time computing,Redundancy (engineering),Dual modular redundancy,Reliability engineering,Memory architecture,Maintenance engineering | Conference |
ISSN | ISBN | Citations |
2163-9612 | 978-1-5090-3220-4 | 0 |
PageRank | References | Authors |
0.34 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keewon Cho | 1 | 18 | 4.64 |
| Jooyoung Kim | 2 | 7 | 1.57 |
| Hayoung Lee | 3 | 5 | 3.14 |
| Sungho Kang | 4 | 436 | 78.44 |