Name
Abstract | ||
|---|---|---|
In view of the numerous clock domain crossings found in modern systems-on-chip and multicore architectures precise metastability characterization is a fundamental task. We propose a conceptually novel approach for the experimental assessment of upset rate over resolution time that is usually employed to extract the relevant characteristics. Our method is based on connecting a time-to-digital converter to the output of the flip flop under test, rather than using a phase shifted clock, as conventionally done. We present the details of an FPGA implementation of our approach and show its feasibility through an experimental evaluation, whose results favorably match those obtained by the conventional method. The benefits of the novel scheme are the ability to perform a calibration for the delay steps, a speed-up of the measurement process, and the availability of a more comprehensive and ordered measurement data set. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/DDECS.2017.7934582 | 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) |
Keywords | Field | DocType |
metastability,time-to-digital converter,TDC,late transition detection,carry chain | Synchronization,Computer science,Field-programmable gate array,Electronic engineering,Real-time computing,Upset,Bandwidth (signal processing),Flip-flop,Time-to-digital converter,Multi-core processor,Calibration | Conference |
ISSN | ISBN | Citations |
2334-3133 | 978-1-5386-0473-1 | 0 |
PageRank | References | Authors |
0.34 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas Polzer | 1 | 49 | 8.43 |
| Florian Huemer | 2 | 3 | 2.46 |
| Andreas Steininger | 3 | 308 | 49.17 |