Name
Abstract | ||
|---|---|---|
In 3DIC design, we may face the problem in manufacturing faults of through silicon vias (TSVs) and microbumps, and it will cause insufficient power delivery and eventually result in fatal error of functioning. In this work, we propose a power TSV/microbump fault tolerance scheme to resolve this issue. First, we use a fast heuristic to predict the worst IR-drop distribution under a given faulty rate by analyzing power simulation results. Next, we use an incremental repair method to enhance power delivery network until reaching the given target IR-drop. The experimental results show that our methodology is effective in power delivery network enhancement in TSV/microbump DFM. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISVLSI.2017.86 | 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | Field | DocType |
Fault tolerance,Power delivery network,3D IC | Power simulation,Heuristic,Electronic engineering,Fault tolerance,Three-dimensional integrated circuit,Engineering,Design for manufacturability,Reliability engineering,Maintenance engineering | Conference |
ISBN | Citations | PageRank |
978-1-5090-6763-3 | 1 | 0.36 |
References | Authors | |
15 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sheng-Hsin Fang | 1 | 1 | 0.69 |
| Chang-Tzu Lin | 2 | 2 | 0.73 |
| Wei-Hsun Liao | 3 | 1 | 0.36 |
| Chien-Chia Huang | 4 | 1 | 1.03 |
| Li-Chin Chen | 5 | 1 | 0.36 |
| Hung-Ming Chen | 6 | 493 | 59.19 |
| I-Hsuan Lee | 7 | 1 | 0.36 |
| Ding-Ming Kwai | 8 | 18 | 2.72 |
| Yung-Fa Chou | 9 | 244 | 23.76 |