Name
Abstract | ||
|---|---|---|
This paper proposes a novel TLB architecture - Deterministic Translation Lookaside Buffer - to reduce TLB misses, energy consumption and effective per access time. DTLB offers tighter upper bound on worst case execution time of real time tasks. This is achieved by backing TLB contents of executing task to PCB on preemption and transferring contents in PCB back to TLB when task resumes its execution. Experimental results carried out using MemSim - a single clock cycle simulator developed in Java with Swing GUI - shows that DTLB gives the least number of TLB misses as compared to conventional TLB model and Reservation based TLB model. DTLB offers on an average 6.74% and 4.91% of dynamic energy savings over conventional model and Reservation based model respectively. Effective access time of DTLB is on an average 2.97% and 2.09% less as compared to conventional and Reservation based model respectively. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/VLSID.2017.50 | 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) |
Keywords | Field | DocType |
TLB,deterministic performance,real-time memory,energy efficiency | Preemption,Worst-case execution time,Access time,Upper and lower bounds,Computer science,Parallel computing,Real-time computing,Memory management,Cycles per instruction,Energy consumption,Translation lookaside buffer,Embedded system | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-1-5090-5741-2 | 0 |
PageRank | References | Authors |
0.34 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kajal Varma | 1 | 0 | 0.34 |
| Geeta Patil | 2 | 1 | 1.03 |
| Biju K Raveendran | 3 | 2 | 5.10 |